1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device incorporating compensation capacitance elements connected between two wirings for compensating a potential variation in wirings.
2. Description of the Related Art
Due to an increase in circuit scale and operation speed of semiconductor devices in recent years, consumption current is increasing. Thus, a variation in supply voltage has been increased. On the other hand, there has been an increasing trend to lower the operating supply voltage for semiconductor devices. In such semiconductor devices, however, since even a slight variation in supply voltage has a great impact on the supply voltage, a problem comes to the surface that the variation in supply voltage causes an unstable circuit operation.
Therefore, it has been proposed that compensation capacitance elements provided between a power supply wiring and a ground wiring of the semiconductor device for suppressing the variation in supply voltage are embedded in the semiconductor device. By embedding the compensation capacitance elements in the semiconductor device in this manner, it is possible to efficiently suppress the variation in supply voltage in the semiconductor device. Japanese Patent Laid-Open Nos. 2004-119857 and 2008-47811 disclose examples of semiconductor devices incorporating compensation capacitance elements.
Japanese Patent Laid-Open No. 2004-119857 discloses a semiconductor device having memory cells and active circuits, in which compensation capacitance elements are formed in regions other than the regions where the memory cells are arranged, and the compensation capacitance elements have almost the same pattern as capacitors of the memory cells. Japanese Patent Laid-Open No. 2008-47811 discloses a semiconductor device on which a Dynamic Random Access Memory (DRAM) region and a logic region are combined, in which compensation capacitance elements are formed in the logic region. As described above, according to these patent documents, the compensation capacitance elements are formed in regions other than the regions where the memory cells are arranged, so that a larger capacitance value is obtained.
However, if the compensation capacitance elements are disposed in the vicinity of signal paths in the case where the compensation capacitance elements are formed in regions other than the regions where the memory cells are arranged, as disclosed in Japanese Patent Laid-Open Nos. 2004-119857 and 2008-47811, parasitic capacitance in the signal paths is increased. The increased parasitic capacitance thus increases signal delay. Such signal delay may cause malfunction of the circuits. In particular, in the semiconductor devices in which the demand for high-speed operation is growing in recent years, the problem of signal delay has become pronounced.